Appendix A. PowerPC Instruction Set Listings A-9 A.2 Instructions Sorted by Opcode Table A-2 lists the instructions defined in the PowerPC architecture in numeric order by opcode. Table A-2. Complete Instruction List Sorted by Opcode 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 Name 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 ---------------------------------------------------------------------------- tdi(*1) 0 0 0 0 1 0 > TO < > A < > SIMM < twi 0 0 0 0 1 1 > TO < > A < > SIMM < mulli 0 0 0 1 1 1 > D < > A < > SIMM < subfic 0 0 1 0 0 0 > D < > A < > SIMM < cmpli 0 0 1 0 1 0 >crD< 0 L > A < > UIMM < cmpi 0 0 1 0 1 1 >crD< 0 L > A < > SIMM < addic 0 0 1 1 0 0 > D < > A < > SIMM < addic. 0 0 1 1 0 1 > D < > A < > SIMM < addi 0 0 1 1 1 0 > D < > A < > SIMM < addis 0 0 1 1 1 1 > D < > A < > SIMM < bcx 0 1 0 0 0 0 > BO < > BI < > BD < A L sc 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 bx 0 1 0 0 1 0 > LI < A L mcrf 0 1 0 0 1 1 >crD< 0 0 >crS< 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bclrx 0 1 0 0 1 1 > BO < > BI < 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 L rfid(*1,*2) 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 crnor 0 1 0 0 1 1 >crbD < >crbA < >crbB < 0 0 0 0 1 0 0 0 0 1 0 rfi(*2,*3) 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 crandc 0 1 0 0 1 1 >crbD < >crbA < >crbB < 0 0 1 0 0 0 0 0 0 1 0 isync 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 crxor 0 1 0 0 1 1 >crbD < >crbA < >crbB < 0 0 1 1 0 0 0 0 0 1 0 crnand 0 1 0 0 1 1 >crbD < >crbA < >crbB < 0 0 1 1 1 0 0 0 0 1 0 crand 0 1 0 0 1 1 >crbD < >crbA < >crbB < 0 1 0 0 0 0 0 0 0 1 0 creqv 0 1 0 0 1 1 >crbD < >crbA < >crbB < 0 1 0 0 1 0 0 0 0 1 0 crorc 0 1 0 0 1 1 >crbD < >crbA < >crbB < 0 1 1 0 1 0 0 0 0 1 0 cror 0 1 0 0 1 1 >crbD < >crbA < >crbB < 0 1 1 1 0 0 0 0 0 1 0 bcctrx 0 1 0 0 1 1 > BO < > BI < 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 L rlwimix 0 1 0 1 0 0 > S < > A < > SH < > MB < > ME < R rlwinmx 0 1 0 1 0 1 > S < > A < > SH < > MB < > ME < R rlwnmx 0 1 0 1 1 1 > S < > A < > B < > MB < > ME < R ori 0 1 1 0 0 0 > S < > A < > UIMM < oris 0 1 1 0 0 1 > S < > A < > UIMM < xori 0 1 1 0 1 0 > S < > A < > UIMM < xoris 0 1 1 0 1 1 > S < > A < > UIMM < andi. 0 1 1 1 0 0 > S < > A < > UIMM < andis. 0 1 1 1 0 1 > S < > A < > UIMM < rldiclx(*1) 0 1 1 1 1 0 > S < > A < > sh < > mb < 0 0 0 s R rldicrx(*1) 0 1 1 1 1 0 > S < > A < > sh < > me < 0 0 1 s R rldicx(*1) 0 1 1 1 1 0 > S < > A < > sh < > mb < 0 1 0 s R rldimix(*1) 0 1 1 1 1 0 > S < > A < > sh < > mb < 0 1 1 s R rldclx(*1) 0 1 1 1 1 0 > S < > A < > B < > mb < 0 1 0 0 0 R rldcrx(*1) 0 1 1 1 1 0 > S < > A < > B < > me < 0 1 0 0 1 R cmp 0 1 1 1 1 1 >crD< 0 L > A < > B < 0 0 0 0 0 0 0 0 0 0 0 tw 0 1 1 1 1 1 > TO < > A < > B < 0 0 0 0 0 0 0 1 0 0 0 subfcx 0 1 1 1 1 1 > D < > A < > B < o 0 0 0 0 0 1 0 0 0 R mulhdux(*1) 0 1 1 1 1 1 > D < > A < > B < 0 0 0 0 0 0 1 0 0 1 R addcx 0 1 1 1 1 1 > D < > A < > B < o 0 0 0 0 0 1 0 1 0 R mulhwux 0 1 1 1 1 1 > D < > A < > B < 0 0 0 0 0 0 1 0 1 1 R mfcr 0 1 1 1 1 1 > D < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 lwarx 0 1 1 1 1 1 > D < > A < > B < 0 0 0 0 0 1 0 1 0 0 0 ldx(*1) 0 1 1 1 1 1 > D < > A < > B < 0 0 0 0 0 1 0 1 0 1 0 lwzx 0 1 1 1 1 1 > D < > A < > B < 0 0 0 0 0 1 0 1 1 1 0 slwx 0 1 1 1 1 1 > S < > A < > B < 0 0 0 0 0 1 1 0 0 0 R cntlzwx 0 1 1 1 1 1 > S < > A < 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 R sldx(*1) 0 1 1 1 1 1 > S < > A < > B < 0 0 0 0 0 1 1 0 1 1 R andx 0 1 1 1 1 1 > S < > A < > B < 0 0 0 0 0 1 1 1 0 0 R cmpl 0 1 1 1 1 1 >crD< 0 L > A < > B < 0 0 0 0 1 0 0 0 0 0 0 subfx 0 1 1 1 1 1 > D < > A < > B < o 0 0 0 1 0 1 0 0 0 R ldux(*1) 0 1 1 1 1 1 > D < > A < > B < 0 0 0 0 1 1 0 1 0 1 0 dcbst 0 1 1 1 1 1 0 0 0 0 0 > A < > B < 0 0 0 0 1 1 0 1 1 0 0 lwzux 0 1 1 1 1 1 > D < > A < > B < 0 0 0 0 1 1 0 1 1 1 0 cntlzdx(*1) 0 1 1 1 1 1 > S < > A < 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 R andcx 0 1 1 1 1 1 > S < > A < > B < 0 0 0 0 1 1 1 1 0 0 R td(*1) 0 1 1 1 1 1 > TO < > A < > B < 0 0 0 1 0 0 0 1 0 0 0 mulhdx(*1) 0 1 1 1 1 1 > D < > A < > B < 0 0 0 1 0 0 1 0 0 1 R mulhwx 0 1 1 1 1 1 > D < > A < > B < 0 0 0 1 0 0 1 0 1 1 R mtsrd(*2,*3) 0 1 1 1 1 1 > S < 0 > SR < 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 mfmsr(*2) 0 1 1 1 1 1 > D < 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 0 ldarx(*1) 0 1 1 1 1 1 > D < > A < > B < 0 0 0 1 0 1 0 1 0 0 0 dcbf 0 1 1 1 1 1 0 0 0 0 0 > A < > B < 0 0 0 1 0 1 0 1 1 0 0 lbzx 0 1 1 1 1 1 > D < > A < > B < 0 0 0 1 0 1 0 1 1 1 0 negx 0 1 1 1 1 1 > D < > A < 0 0 0 0 0 O 0 0 1 1 0 1 0 0 0 R mtsrdin(*23) 0 1 1 1 1 1 > S < 0 0 0 0 0 > B < 0 0 0 1 1 1 0 0 1 0 0 lbzux 0 1 1 1 1 1 > D < > A < > B < 0 0 0 1 1 1 0 1 1 1 0 norx 0 1 1 1 1 1 > S < > A < > B < 0 0 0 1 1 1 1 1 0 0 R subfex 0 1 1 1 1 1 > D < > A < > B < o 0 1 0 0 0 1 0 0 0 R addex 0 1 1 1 1 1 > D < > A < > B < o 0 1 0 0 0 1 0 1 0 R mtcrf 0 1 1 1 1 1 > S < 0 > CRM < 0 0 0 1 0 0 1 0 0 0 0 0 mtmsr(*2,*3) 0 1 1 1 1 1 > S < 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 stdx(*1) 0 1 1 1 1 1 > S < > A < > B < 0 0 1 0 0 1 0 1 0 1 0 stwcx. 0 1 1 1 1 1 > S < > A < > B < 0 0 1 0 0 1 0 1 1 0 1 stwx 0 1 1 1 1 1 > S < > A < > B < 0 0 1 0 0 1 0 1 1 1 0 mtmsrd(*1,2) 0 1 1 1 1 1 > S < 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 0 stdux(*1) 0 1 1 1 1 1 > S < > A < > B < 0 0 1 0 1 1 0 1 0 1 0 stwux 0 1 1 1 1 1 > S < > A < > B < 0 0 1 0 1 1 0 1 1 1 0 subfzex 0 1 1 1 1 1 > D < > A < 0 0 0 0 0 o 0 1 1 0 0 1 0 0 0 R addzex 0 1 1 1 1 1 > D < > A < 0 0 0 0 0 o 0 1 1 0 0 1 0 1 0 R mtsr(*2,*3) 0 1 1 1 1 1 > S < 0 > SR < 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 stdcx.(*1) 0 1 1 1 1 1 > S < > A < > B < 0 0 1 1 0 1 0 1 1 0 1 stbx 0 1 1 1 1 1 > S < > A < > B < 0 0 1 1 0 1 0 1 1 1 0 subfmex 0 1 1 1 1 1 > D < > A < 0 0 0 0 0 o 0 1 1 1 0 1 0 0 0 R mulld(*1) 0 1 1 1 1 1 > D < > A < > B < o 0 1 1 1 0 1 0 0 1 R addmex 0 1 1 1 1 1 > D < > A < 0 0 0 0 0 o 0 1 1 1 0 1 0 1 0 R mullwx 0 1 1 1 1 1 > D < > A < > B < o 0 1 1 1 0 1 0 1 1 R mtsrin(*2,3) 0 1 1 1 1 1 > S < 0 0 0 0 0 > B < 0 0 1 1 1 1 0 0 1 0 0 dcbtst 0 1 1 1 1 1 0 0 0 0 0 > A < > B < 0 0 1 1 1 1 0 1 1 0 0 stbux 0 1 1 1 1 1 > S < > A < > B < 0 0 1 1 1 1 0 1 1 1 0 addx 0 1 1 1 1 1 > D < > A < > B < o 1 0 0 0 0 1 0 1 0 R dcbt 0 1 1 1 1 1 0 0 0 0 0 > A < > B < 0 1 0 0 0 1 0 1 1 0 0 lhzx 0 1 1 1 1 1 > D < > A < > B < 0 1 0 0 0 1 0 1 1 1 0 eqvx 0 1 1 1 1 1 > S < > A < > B < 0 1 0 0 0 1 1 1 0 0 R tlbie(*2,4) 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 > B < 0 1 0 0 1 1 0 0 1 0 0 eciwx 0 1 1 1 1 1 > D < > A < > B < 0 1 0 0 1 1 0 1 1 0 0 lhzux 0 1 1 1 1 1 > D < > A < > B < 0 1 0 0 1 1 0 1 1 1 0 xorx 0 1 1 1 1 1 > S < > A < > B < 0 1 0 0 1 1 1 1 0 0 R mfspr(*5) 0 1 1 1 1 1 > D < > spr < 0 1 0 1 0 1 0 0 1 1 0 lwax(*1) 0 1 1 1 1 1 > D < > A < > B < 0 1 0 1 0 1 0 1 0 1 0 lhax 0 1 1 1 1 1 > D < > A < > B < 0 1 0 1 0 1 0 1 1 1 0 tlbia(2,4,7) 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 0 0 mftb 0 1 1 1 1 1 > D < > tbr < 0 1 0 1 1 1 0 0 1 1 0 lwaux(*1) 0 1 1 1 1 1 > D < > A < > B < 0 1 0 1 1 1 0 1 0 1 0 lhaux 0 1 1 1 1 1 > D < > A < > B < 0 1 0 1 1 1 0 1 1 1 0 sthx 0 1 1 1 1 1 > S < > A < > B < 0 1 1 0 0 1 0 1 1 1 0 orcx 0 1 1 1 1 1 > S < > A < > B < 0 1 1 0 0 1 1 1 0 0 R sradix(*1) 0 1 1 1 1 1 > S < > A < > sh < 0 1 1 0 1 0 1 1 1 s R slbie(1,2,4) 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 > B < 0 1 1 0 1 1 0 0 1 0 0 ecowx 0 1 1 1 1 1 > S < > A < > B < 0 1 1 0 1 1 0 1 1 0 0 sthux 0 1 1 1 1 1 > S < > A < > B < 0 1 1 0 1 1 0 1 1 1 0 orx 0 1 1 1 1 1 > S < > A < > B < 0 1 1 0 1 1 1 1 0 0 R divdux(*1) 0 1 1 1 1 1 > D < > A < > B < o 1 1 1 0 0 1 0 0 1 R divwux 0 1 1 1 1 1 > D < > A < > B < o 1 1 1 0 0 1 0 1 1 R mtspr(*5) 0 1 1 1 1 1 > S < > spr < 0 1 1 1 0 1 0 0 1 1 0 dcbi(*2) 0 1 1 1 1 1 0 0 0 0 0 > A < > B < 0 1 1 1 0 1 0 1 1 0 0 nandx 0 1 1 1 1 1 > S < > A < > B < 0 1 1 1 0 1 1 1 0 0 R divdx(*1) 0 1 1 1 1 1 > D < > A < > B < o 1 1 1 1 0 1 0 0 1 R divwx 0 1 1 1 1 1 > D < > A < > B < o 1 1 1 1 0 1 0 1 1 R slbia(1,2,4) 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 mcrxr 0 1 1 1 1 1 >crD< 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 lswx(*6) 0 1 1 1 1 1 > D < > A < > B < 1 0 0 0 0 1 0 1 0 1 0 lwbrx 0 1 1 1 1 1 > D < > A < > B < 1 0 0 0 0 1 0 1 1 0 0 lfsx 0 1 1 1 1 1 > D < > A < > B < 1 0 0 0 0 1 0 1 1 1 0 srwx 0 1 1 1 1 1 > S < > A < > B < 1 0 0 0 0 1 1 0 0 0 R srdx(*1) 0 1 1 1 1 1 > S < > A < > B < 1 0 0 0 0 1 1 0 1 1 R tlbsync(2,4) 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 1 0 0 lfsux 0 1 1 1 1 1 > D < > A < > B < 1 0 0 0 1 1 0 1 1 1 0 mfsr(2,3) 0 1 1 1 1 1 > D < 0 > SR < 0 0 0 0 0 1 0 0 1 0 1 0 0 1 1 0 lswi(*6) 0 1 1 1 1 1 > D < > A < > NB < 1 0 0 1 0 1 0 1 0 1 0 sync 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 0 0 lfdx 0 1 1 1 1 1 > D < > A < > B < 1 0 0 1 0 1 0 1 1 1 0 lfdux 0 1 1 1 1 1 > D < > A < > B < 1 0 0 1 1 1 0 1 1 1 0 mfsrin(2,3) 0 1 1 1 1 1 > D < 0 0 0 0 0 > B < 1 0 1 0 0 1 0 0 1 1 0 stswx(*6) 0 1 1 1 1 1 > S < > A < > B < 1 0 1 0 0 1 0 1 0 1 0 stwbrx 0 1 1 1 1 1 > S < > A < > B < 1 0 1 0 0 1 0 1 1 0 0 stfsx 0 1 1 1 1 1 > S < > A < > B < 1 0 1 0 0 1 0 1 1 1 0 stfsux 0 1 1 1 1 1 > S < > A < > B < 1 0 1 0 1 1 0 1 1 1 0 stswi(*6) 0 1 1 1 1 1 > S < > A < > NB < 1 0 1 1 0 1 0 1 0 1 0 stfdx 0 1 1 1 1 1 > S < > A < > B < 1 0 1 1 0 1 0 1 1 1 0 dcba(*4,7) 0 1 1 1 1 1 0 0 0 0 0 > A < > B < 1 0 1 1 1 1 0 1 1 0 0 stfdux 0 1 1 1 1 1 > S < > A < > B < 1 0 1 1 1 1 0 1 1 1 0 lhbrx 0 1 1 1 1 1 > D < > A < > B < 1 1 0 0 0 1 0 1 1 0 0 srawx 0 1 1 1 1 1 > S < > A < > B < 1 1 0 0 0 1 1 0 0 0 R sradx(*1) 0 1 1 1 1 1 > S < > A < > B < 1 1 0 0 0 1 1 0 1 0 R srawix 0 1 1 1 1 1 > S < > A < > SH < 1 1 0 0 1 1 1 0 0 0 R eieio 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 0 sthbrx 0 1 1 1 1 1 > S < > A < > B < 1 1 1 0 0 1 0 1 1 0 0 extshx 0 1 1 1 1 1 > S < > A < 0 0 0 0 0 1 1 1 0 0 1 1 0 1 0 R extsbx 0 1 1 1 1 1 > S < > A < 0 0 0 0 0 1 1 1 0 1 1 1 0 1 0 R icbi 0 1 1 1 1 1 0 0 0 0 0 > A < > B < 1 1 1 1 0 1 0 1 1 0 0 stfiwx(*4) 0 1 1 1 1 1 > S < > A < > B < 1 1 1 1 0 1 0 1 1 1 0 extsw(*1) 0 1 1 1 1 1 > S < > A < 0 0 0 0 0 1 1 1 1 0 1 1 0 1 0 R dcbz 0 1 1 1 1 1 0 0 0 0 0 > A < > B < 1 1 1 1 1 1 0 1 1 0 0 lwz 1 0 0 0 0 0 > D < > A < > d < lwzu 1 0 0 0 0 1 > D < > A < > d < lbz 1 0 0 0 1 0 > D < > A < > d < lbzu 1 0 0 0 1 1 > D < > A < > d < stw 1 0 0 1 0 0 > S < > A < > d < stwu 1 0 0 1 0 1 > S < > A < > d < stb 1 0 0 1 1 0 > S < > A < > d < stbu 1 0 0 1 1 1 > S < > A < > d < lhz 1 0 1 0 0 0 > D < > A < > d < lhzu 1 0 1 0 0 1 > D < > A < > d < lha 1 0 1 0 1 0 > D < > A < > d < lhau 1 0 1 0 1 1 > D < > A < > d < sth 1 0 1 1 0 0 > S < > A < > d < sthu 1 0 1 1 0 1 > S < > A < > d < lmw(*6) 1 0 1 1 1 0 > D < > A < > d < stmw(*6) 1 0 1 1 1 1 > S < > A < > d < lfs 1 1 0 0 0 0 > D < > A < > d < lfsu 1 1 0 0 0 1 > D < > A < > d < lfd 1 1 0 0 1 0 > D < > A < > d < lfdu 1 1 0 0 1 1 > D < > A < > d < stfs 1 1 0 1 0 0 > S < > A < > d < stfsu 1 1 0 1 0 1 > S < > A < > d < stfd 1 1 0 1 1 0 > S < > A < > d < stfdu 1 1 0 1 1 1 > S < > A < > d < ld(*1) 1 1 1 0 1 0 > D < > A < > ds < 0 0 ldu(*1) 1 1 1 0 1 0 > D < > A < > ds < 0 1 lwa(*1) 1 1 1 0 1 0 > D < > A < > ds < 1 0 fdivsx 1 1 1 0 1 1 > D < > A < > B < 0 0 0 0 0 1 0 0 1 0 R fsubsx 1 1 1 0 1 1 > D < > A < > B < 0 0 0 0 0 1 0 1 0 0 R faddsx 1 1 1 0 1 1 > D < > A < > B < 0 0 0 0 0 1 0 1 0 1 R fsqrtsx(4,7) 1 1 1 0 1 1 > D < 0 0 0 0 0 > B < 0 0 0 0 0 1 0 1 1 0 R fresx(*4) 1 1 1 0 1 1 > D < 0 0 0 0 0 > B < 0 0 0 0 0 1 1 0 0 0 R fmulsx 1 1 1 0 1 1 > D < > A < 0 0 0 0 0 > C < 1 1 0 0 1 R fmsubsx 1 1 1 0 1 1 > D < > A < > B < > C < 1 1 1 0 0 R fmaddsx 1 1 1 0 1 1 > D < > A < > B < > C < 1 1 1 0 1 R fnmsubsx 1 1 1 0 1 1 > D < > A < > B < > C < 1 1 1 1 0 R fnmaddsx 1 1 1 0 1 1 > D < > A < > B < > C < 1 1 1 1 1 R std(*1) 1 1 1 1 1 0 > S < > A < > ds < 0 0 stdu(*1) 1 1 1 1 1 0 > S < > A < > ds < 0 1 fcmpu 1 1 1 1 1 1 >crD< 0 0 > A < > B < 0 0 0 0 0 0 0 0 0 0 0 frspx 1 1 1 1 1 1 > D < 0 0 0 0 0 > B < 0 0 0 0 0 0 1 1 0 0 R fctiwx 1 1 1 1 1 1 > D < 0 0 0 0 0 > B < 0 0 0 0 0 0 1 1 1 0 R fctiwzx 1 1 1 1 1 1 > D < 0 0 0 0 0 > B < 0 0 0 0 0 0 1 1 1 1 R fdivx 1 1 1 1 1 1 > D < > A < > B < 0 0 0 0 0 1 0 0 1 0 R fsubx 1 1 1 1 1 1 > D < > A < > B < 0 0 0 0 0 1 0 1 0 0 R faddx 1 1 1 1 1 1 > D < > A < > B < 0 0 0 0 0 1 0 1 0 1 R fsqrtx(*4,7) 1 1 1 1 1 1 > D < 0 0 0 0 0 > B < 0 0 0 0 0 1 0 1 1 0 R fselx(*4) 1 1 1 1 1 1 > D < > A < > B < > C < 1 0 1 1 1 R fmulx 1 1 1 1 1 1 > D < > A < 0 0 0 0 0 > C < 1 1 0 0 1 R frsqrtex(*4) 1 1 1 1 1 1 > D < 0 0 0 0 0 > B < 0 0 0 0 0 1 1 0 1 0 R fmsubx 1 1 1 1 1 1 > D < > A < > B < > C < 1 1 1 0 0 R fmaddx 1 1 1 1 1 1 > D < > A < > B < > C < 1 1 1 0 1 R fnmsubx 1 1 1 1 1 1 > D < > A < > B < > C < 1 1 1 1 0 R fnmaddx 1 1 1 1 1 1 > D < > A < > B < > C < 1 1 1 1 1 R fcmpo 1 1 1 1 1 1 >crD< 0 0 > A < > B < 0 0 0 0 1 0 0 0 0 0 0 mtfsb1x 1 1 1 1 1 1 >crbD < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 R fnegx 1 1 1 1 1 1 > D < 0 0 0 0 0 > B < 0 0 0 0 1 0 1 0 0 0 R mcrfs 1 1 1 1 1 1 >crD< 0 0 >crS< 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 mtfsb0x 1 1 1 1 1 1 >crbD < 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 R fmrx 1 1 1 1 1 1 > D < 0 0 0 0 0 > B < 0 0 0 1 0 0 1 0 0 0 R mtfsfix 1 1 1 1 1 1 >crD< 0 0 0 0 0 0 0 > IMM < 0 0 0 1 0 0 0 0 1 1 0 R fnabsx 1 1 1 1 1 1 > D < 0 0 0 0 0 > B < 0 0 1 0 0 0 1 0 0 0 R fabsx 1 1 1 1 1 1 > D < 0 0 0 0 0 > B < 0 1 0 0 0 0 1 0 0 0 R mffsx 1 1 1 1 1 1 > D < 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 R mtfsfx 1 1 1 1 1 1 0 > FM < 0 > B < 1 0 1 1 0 0 0 1 1 1 R fctidx(*1) 1 1 1 1 1 1 > D < 0 0 0 0 0 > B < 1 1 0 0 1 0 1 1 1 0 R fctidzx(*1) 1 1 1 1 1 1 > D < 0 0 0 0 0 > B < 1 1 0 0 1 0 1 1 1 1 R fcfidx(*1) 1 1 1 1 1 1 > D < 0 0 0 0 0 > B < 1 1 0 1 0 0 1 1 1 0 R ---------------------------------------------------------------------------- 1 64-bit instruction 2 Supervisor-level instruction 3 Optional 64-bit bridge instruction 4 Optional instruction 5 Supervisor- and user-level instruction 6 Load/store string/multiple instruction 7 32-bit instruction not implemented by the MPC750